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Strabag a.s.Praha, TschechienASIC / FPGA Semiconductor Design Trainee / Internship
HoneywellPrague, PRAHA, Czech RepublicJOB DESCRIPTION
Innovate to solve the world's most important challenges
We have an opportunity for an Engineering Support Intern to join us at Honeywell, in Prague, where you will be responsible for working on digital design using System Verilog, support activities as integration and testing. This is a hybrid role, 3 + 2 model.
Since the invention of autopilot in 1914, we’ve been a leader in innovation for the Air Travel industry. Today, thousands of Honeywell products are used in aircraft and airports around the world. Everyday 140,000 Honeywell air turbine starters bring to life commercial and military aircraft, industrial and marine equipment.
Key responsibilities
- ASIC / FPGA digital design & verification
- Working with HDL languages (System Verilog, VHDL, Verilog)
- Utilizing FPGA / SOC technologies – Microchip, AMD (XILINX), Intel, etc.
- Supporting the team in the development of Safety / Mission critical digital systems for Avionics and & Space applications per DO-254 standard
- Engaging with full ASIC / FPGA development process (from requirement definition, to design, verification, synthesis, STA, CDC, preparing technical documentation)
Please note that due to export restrictions, we will only be able to take into consideration applicants with an EU citizenship.
Key skills and qualifications
Our offer :
We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
Innovate to solve the world's most important challenges, join us now!
FutureShaper
EMEAUR